The use of multiple-threshold and multiple gate length devices on a chip has become popular in IC design for handling the trade-off between speed and leakage power. These techniques are now being combined with other low-power techniques such as voltage scaling for further reducing system power.
Voltage scaling has a non-linear effect on delay (and power) for gates consisting of different threshold devices. These differences can cause difficulties in closing timing requirements for systems employing voltage scaling, where the worst-case critical path may depend on the specific supply voltage used.
This delay variability is compounded by process variability which is becoming more significant as device dimensions shrink, and also affects the various threshold and gate length devices differently, decreasing the correlation between the variation of characteristics (such as delay) of those circuits.